diff --git a/src/include/storage/barrier.h b/src/include/storage/barrier.h
index 33a6d4ee689c65f6995458296468ca78fcce8ea2..cde9cf7d0e324b109e1fd73662097cd7b541e201 100644
--- a/src/include/storage/barrier.h
+++ b/src/include/storage/barrier.h
@@ -53,7 +53,12 @@ extern slock_t dummy_spinlock;
 /*
  * icc defines __GNUC__, but doesn't support gcc's inline asm syntax
  */
+#if defined(__ia64__) || defined(__ia64)
+#define pg_memory_barrier()		__mf()
+#elif defined(__i386__) || defined(__x86_64__)
 #define pg_memory_barrier()		_mm_mfence()
+#endif
+
 #define pg_compiler_barrier()	__memory_barrier()
 #elif defined(__GNUC__)
 
@@ -112,8 +117,12 @@ extern slock_t dummy_spinlock;
  * read barrier to cover that case.  We might need to add that later.
  */
 #define pg_memory_barrier()		__asm__ __volatile__ ("mb" : : : "memory")
-#define pg_read_barrier()		__asm__ __volatile__ ("rmb" : : : "memory")
+#define pg_read_barrier()		__asm__ __volatile__ ("mb" : : : "memory")
 #define pg_write_barrier()		__asm__ __volatile__ ("wmb" : : : "memory")
+#elif defined(__hppa) || defined(__hppa__)		/* HP PA-RISC */
+
+/* HPPA doesn't do either read or write reordering */
+#define pg_memory_barrier()		pg_compiler_barrier()
 #elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1)
 
 /*
@@ -148,7 +157,7 @@ extern slock_t dummy_spinlock;
  * fence.  But all of our actual implementations seem OK in this regard.
  */
 #if !defined(pg_memory_barrier)
-#define pg_memory_barrier(x) \
+#define pg_memory_barrier() \
 	do { S_LOCK(&dummy_spinlock); S_UNLOCK(&dummy_spinlock); } while (0)
 #endif