From aac3c301b5e8178841e5749b3657c1a639ba06c1 Mon Sep 17 00:00:00 2001
From: Tom Lane <tgl@sss.pgh.pa.us>
Date: Mon, 27 Jul 2009 05:31:05 +0000
Subject: [PATCH] Add s_lock support for SuperH architecture.
After a patch originally submitted by Nobuhiro Iwamatsu, but corrected
(I think) to match our guidelines for safe use of asm fragments.
This should be considered untested ...
---
src/include/storage/s_lock.h | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
index 534543eed31..174fa60d6ec 100644
--- a/src/include/storage/s_lock.h
+++ b/src/include/storage/s_lock.h
@@ -66,7 +66,7 @@
* Portions Copyright (c) 1996-2009, PostgreSQL Global Development Group
* Portions Copyright (c) 1994, Regents of the University of California
*
- * $PostgreSQL: pgsql/src/include/storage/s_lock.h,v 1.166 2009/01/01 17:24:01 momjian Exp $
+ * $PostgreSQL: pgsql/src/include/storage/s_lock.h,v 1.167 2009/07/27 05:31:05 tgl Exp $
*
*-------------------------------------------------------------------------
*/
@@ -568,6 +568,36 @@ typedef int slock_t;
#endif /* __m32r__ */
+#if defined(__sh__) /* Renesas' SuperH */
+#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
+#define TAS(lock) tas(lock)
+
+static __inline__ int
+tas(volatile slock_t *lock)
+{
+ register int _res;
+
+ /*
+ * This asm is coded as if %0 could be any register, but actually SuperH
+ * restricts the target of xor-immediate to be R0. That's handled by
+ * the "z" constraint on _res.
+ */
+ __asm__ __volatile__(
+ " tas.b @%2 \n"
+ " movt %0 \n"
+ " xor #1,%0 \n"
+: "=z"(_res), "+m"(*lock)
+: "r"(lock)
+: "memory", "t");
+ return _res;
+}
+
+#endif /* __sh__ */
+
+
/* These live in s_lock.c, but only for gcc */
--
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